Intel Corporation v. Tela Innovations, Inc.

Background

The case involves six patents assigned to Tela Innovations, Inc. and asserted against Intel Corporation. The patents concern integrated-circuit design and manufacturing, including ways to manage the “lithographic gap”—the difference between shrinking semiconductor features and the wavelength of light used to create those features.

Intel filed this declaratory-judgment action on May 15, 2018. The parties asked the court to interpret seven terms in the asserted patent claims. They agreed on the meanings of “diffusion region” and “a lithography process,” so the court addressed the seven disputed terms after briefing and a September 27, 2019 hearing.

Legal standard

Claim construction is the court’s interpretation of patent-claim language. The court generally gives a term its ordinary and customary meaning to a person of ordinary skill in the relevant technical field at the time of the invention. It considers the claim language, the patent specification, and, when available, the patent’s prosecution history. The court may also consider reliable outside evidence, but that evidence cannot contradict the meaning shown by the patent and its prosecution history.

Rulings on the disputed terms

1. “Linear gate electrode segment,” “linear conductor segment(s),” “linear conductive segment(s),” and “(interconnect) linear conductive structures.” The court construed these terms to mean “extending in a single direction over the substrate.” It rejected Intel’s proposed requirement that the structures have a consistent vertical cross-section. The court reasoned that the patents focus on whether a feature is straight in the x-y plane and do not clearly disclaim structures with different cross-sectional shapes.

2. “Gate structure(s)” and “gate electrode feature(s).” The court construed these terms to mean “feature comprising a gate(s) of a transistor(s) or a dummy gate.” It rejected Intel’s proposed requirement that these features be linear and declined to require them to be defined below a gate contact. The court explained that a dummy gate cannot form a transistor gate because it lacks a source or drain, and some gate structures may not have an associated gate contact.

3. “Gate electrode.” The court construed this term to mean “a portion of the conductive shape in the gate layer that extends over the diffusion region and is used to control the flow of electrical current between the source and drain regions of a transistor.” The court included the requirement that the electrode extend over a diffusion region but rejected Intel’s proposed requirement that it be parallel to that region.

4. “Gate electrode contact,” “gate contact structure(s),” and “contact structure.” The court construed these terms to mean “conductive structure(s) in a gate contact layer above and separate from the gate layer and below and separate from interconnect layers.” The court concluded that the contact structures occupy a separate layer between the gate layer and the interconnect layers. The construction did not eliminate the possibility that the structures physically contact the gate and interconnect features.

5. “Interconnect level region.” The court construed this term to mean “an area within a layer having conductive structures where the layer is located above the diffusion contact layer/gate electrode contact layer and enables definition of the desired circuit connectivity.” The court specified that the interconnect level region is above the gate contacts and does not include the distinct gate electrode layer. It rejected a narrower proposal that would have limited interconnects to metal and via structures.

6. “[Gate / metal / contact] gridline(s).” The court construed this term to mean “virtual projected lines along which [gate / metal / contact] features are positioned.” The court used “positioned” rather than “defined” or “formed” to describe the features’ relationship to virtual gridlines during layout and fabrication.

7. “Physically and electrically separated by a [conductor] line end spacing of minimum size.” The court held this term indefinite. Indefiniteness means that the patent does not inform skilled people, with reasonable certainty, about the scope of the claim. The court found that the patent explains where the spacing is located and why minimizing it is desirable, but does not provide an objective boundary for deciding what qualifies as “minimum size.” The court rejected Tela’s argument that semiconductor design rules supplied that boundary.

Disposition and significance

The court entered the stated constructions for all seven disputed terms and found the line-end-spacing term indefinite. This was a claim-construction ruling; the opinion did not state that it entered a final judgment on Intel’s or Tela’s ultimate infringement claims.